AMD Developer Hackathon 2026

A language model that
thinks in silicon

vlsi-moe-yarn is a domain-specialized LLM for VLSI and chip design — RTL generation, timing constraints, verification, and architecture reasoning across a 262K-token context window.

View Model on HF GitHub
262K
Token context
MoE
Architecture
6
Specialized agents
MI300X
AMD GPU

Capabilities

Purpose-built for chip design

Standard LLMs fail at VLSI tasks — they lack RTL-specific knowledge, lose coherence on long specs, and hallucinate timing numbers. vlsi-moe-yarn is trained on a VLSI-domain corpus via knowledge distillation, with YaRN context extension to hold an entire SoC specification in a single pass.

⚡
RTL Design
Verilog & SystemVerilog generation, review, and bug detection. Parameterized modules, FSMs, pipelines.
🏗️
Architecture
NoC topology, pipeline microarchitecture, memory hierarchy decisions, and SoC integration planning.
⏱️
Timing & CDC
Clock-domain crossing analysis, synchronizer design, hold/setup violation detection and correction.
📐
Constraints
SDC and UPF generation, floorplan guidance, power intent specification, and multi-corner analysis.
🧪
Verification
Testbench generation, functional coverage reasoning, assertion writing, and simulation analysis.
📄
Documentation
Q&A over full datasheets up to 262K tokens. Spec comprehension, design doc generation.

AgentIC Pipeline

Six agents. One backbone.

AgentIC is a multi-agent orchestration framework where each specialized agent calls vlsi-moe-yarn as its reasoning engine. The 262K context window carries full design state across the entire pipeline without losing earlier decisions.

Agent Roster

All agents use vlsi-moe-yarn via OpenAI-compatible API

Architect
architect.py
High-level block decomposition and architecture decisions
Designer
designer.py
RTL Verilog / SystemVerilog code generation
SDC Agent
sdc_agent.py
Timing constraint and clock definition generation
Testbench
testbench_designer.py
Automated testbench and stimulus generation
Verifier
verifier.py
Functional verification reasoning and coverage
Doc Agent
doc_agent.py
Design documentation and spec writing

Usage

OpenAI-compatible API

The model is served via vLLM on AMD Instinct MI300X with full OpenAI-compatible endpoints. Drop it into any agent framework with zero code changes.

python · connect to vlsi-moe-yarn
from openai import OpenAI

# Drop-in OpenAI client — just change base_url
client = OpenAI(
    base_url="http://YOUR_SERVER:8000/v1",
    api_key="EMPTY",
)

response = client.chat.completions.create(
    model="vlsi-moe-yarn",
    messages=[
        {"role": "system", "content": "You are a VLSI design expert."},
        {"role": "user",   "content": "Generate a parameterized FIFO in SystemVerilog."}
    ],
    max_tokens=1024,
)
print(response.choices[0].message.content)

Architecture

Model specs

PropertyValue
BaseQwen encoder-decoder backbone
Modification10% of FFN layers → reasoning-optimized FFN blocks
Context extensionYaRN Yet another RoPE extensioN
Max context262,144 tokens
dtypebfloat16 · fp8 KV cache
Training methodKnowledge distillation on VLSI-domain corpus
Inference enginevLLM v0.17.1
HardwareAMD Instinct MI300X (192 GB HBM3)

Hugging Face

Model repository

The full model weights, model card, and technical details are hosted on Hugging Face.

🤗 vxkyyy / vlsi-moe-yarn

Model weights · Model card · Architecture details · License: MIT

🔬 VLSI ⚡ RTL 262K context MoE · YaRN AMD MI300X
Open Model Repo →